The present invention relates to semiconductor devices and more particularly to technology for a semiconductor device with a semiconductor chip mounted over a wiring substrate.
Japanese Unexamined Patent Application Publication No. 2009-70965 and Japanese Unexamined Patent Application Publication No. 2010-129716 each describe a semiconductor device including a package with a memory chip mounted over the package in which a microcomputer chip (or a semiconductor chip with a logic circuit) is mounted.
Japanese Unexamined Patent Application Publication No. 2009-70965 describes a configuration in which a testing pad for checking the conduction state between a microcomputer chip and a memory chip is arranged outside the lower surface of the wiring substrate of a lower package.
Japanese Unexamined Patent Application Publication No. 2010-129716 describes a configuration in which a bump for checking the connection between a lower semiconductor chip and an upper package and a bump for checking the connection with the upper package without the mediation of the lower semiconductor chip are arranged outside the lower surface of the wiring substrate of the lower package.